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CS 572 Micro ArchitectureFall 2011TTH 17:30-18:45, EBA 254 San Diego State University
Instructor: Dr. Tao Xie GMCS 544, 619-594-2014 Office hours: TTH 4 pm - 5 pm. |
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Date |
Topics |
Reading Assignments |
Slides |
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8/30/11 |
Introduction |
Ch 1.1-1.6 |
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9/01/11 |
Performance Measurement |
Ch 1.8-1.9 |
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9/06/11 |
Instruction Set Architecture |
B.1-B.3, B.4, B.5 |
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9/08/11 |
Instruction Set Architecture: MIPS1 |
B.6, B.7, B.9 |
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9/13/11 |
Instruction Set Architecture: MIPS2 |
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9/15/11 |
Single-Cycle Processor Implementation1 |
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9/20/11 |
Single-Cycle Processor Implementation2 |
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9/22/11 |
Multi-Cycle Processor Implementation 1 |
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9/27/11 |
Multi-Cycle Processor Implementation 2 |
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10/04/11 |
Pipeline: Introduction |
A.1 |
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10/06/11 |
Pipeline: Structural Hazards |
A.2 |
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10/11/11 |
Pipeline: Data Hazards |
A.3 |
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10/18/11 |
Pipeline: Branch Prediction |
A.3 |
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10/20/11 |
Exercise Class |
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10/25/11 |
Review session for midterm exam |
The Study Guide for the Midterm exam |
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10/27/11 |
Midterm |
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11/01/11 |
Midterm Summary Session |
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11/03/11 |
Pipeline: Exceptions, control |
A.4 |
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11/08/11 |
Instruction-level parallelism: Introduction |
Ch2.1 |
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11/10/11 |
Instruction-level parallelism: Scoreboard |
A.7 |
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11/15/11 |
Tomasulo’s Algorithm: Introduction and Example |
Ch2.4-Ch2.5 |
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11/17/11 |
Tomasulo’s Algorithm: A loop example |
Ch2.5 |
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11/22/11 |
Tomasulo’s Algorithm: Reorder Buffer |
Ch2.6 |
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11/29/11 |
Memory Hierarchy: Set Associative Cache |
Ch5.1-Ch5.2 |
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12/01/11 |
Memory Hierarchy: Cache Performance |
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12/06/11 |
Storage Systems and I/O Topics |
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12/08/11 |
Final Review |
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Thursday, Dec. 15 |
Final Exam (15:30 - 17:30) |
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