CS370 -
Computer Architecture
Spring 2003
Instructor : Shobha M. Subbaramoo email : shobha@san.rr.com
Textbook : “Logic and Computer Design Fundementals” - M. Morris Mano and Charles R. Kime. 2nd Edition Updated (ISBN: 0130124680, Publisher: Prentice Hall)
Prerequisites:
Knowledge
of C language or Good programming concepts in general.
Logic gates, combinational
circuits, sequential circuits, memory and bus system, control unit, CPU,
exception processing, traps and interrupts, input-output and communication,
reduced instruction set computers, use of simulators for analysis and design of
computer circuits, and traps/interrupts.
Introduction (1/2 week)
About the subject, Levels of abstraction of digital systems (transistor, gate, register, processor). Design and analysis of digital systems. CAD tools
Data types and representation (1 week)
Binary coding and conversions between different number systems. Ones, two's complement, sign magnitude representation. Adding, subtracting and multiplication of binary numbers. Fixed and floating-point representation. Error detection and correction (cube representation of binary strings, Hamming code)
Boolean algebra and logic design (2 weeks)
Axiomatic definition of Boolean algebra. Boolean operators and duality principle
Theorems of Boolean algebra. Boolean functions and expression equivalence
Minterms and maxterms (standard forms of Boolean functions). Sixteen binary logic operations . Digital logic gates and example of full-adder . Design with NAND/NOR gates, complex gates. Custom design (gate arrays, FPGA).
Simplification of Boolean functions (1 ˝ weeks)
Karnuagh maps (1,2,3, 4 and 5 –variable maps). Selection of prime implicants. Don't care conditions. Technology mapping for gate arrays (standard to NAND/NOR schemes, standard to gate arrays. Timing issues. Static and dynamic hazard.
Combinatorial circuits (2 weeks)
Ripple-carry serial adder. Carry-look-ahead generator. CLA adder. Twos' complement adder subtractor. Arithmetic-logic unit. Decoders . Multiplexers. Priority encoders. Magnitude comparators. Shifters (including barrel shifters). ROM. Programmable logic arrays. Full adder with ROM, PLA
Sequential circuits (3 weeks)
SR-latch (NOR, NAND implementation). Gated SR-latch, Gated D-latch. Flip-flops. Master-slave FF, Edge triggered FF. FF types (SR, JK, D, T). Design of sequential circuits (analysis and synthesis with state tables). Shift registers. Serial adders. Counters (ripple, synchronous).
Storage components (1 week)
Simple RAM (coincident decoding). Array of RAM chips (extending the address space and the word size). Push-down stack. FIFO queue. Memory timing . Implementation of error detection and correction. ROM.
Processor (2 weeks)
Register transfer micro operations . Register transfer language. Arithmetic micro operations. Logic micro operations. ALU and shifter unit. Datapaths. Bus transfer
Processor unit . Control unit (hardwired and micro programmed). Micro programs and micro routines. Instruction set and addressing modes. Complex instruction set vs. RISC. Reduced instruction set – a 32-bit example. Data-forwarding and branch prediction.
System bus (2 weeks)
Synchronous bus control. Asynchronous bus control. Connecting memory to CPU
Implementation of interrupts. Vectored interrupts and autovectored interrupts.
Programming with traps and interrupts
1 or 2 non-programming assignments
3 programming assignments
Assignments 30%
Midterm exams 35%
Final exam 35%